projects:ep32:start
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projects:ep32:start [2017-04-16 10:49] – [EP32 Processor for FPGA] mka | projects:ep32:start [2017-09-19 22:20] (aktuell) – [Regarding Forth] mka | ||
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- | ====== EP32 Processor for FPGA ====== | + | ====== EP32 – 32 Bit RISC Processor for FPGA ====== |
- | The 32 Bit EP32 Processor for FPGA may be combined with eForth. You my order the VHDL and documentation for print from Ting directly, cost is $25. | + | The 32 Bit EP32 Processor for FPGA may be combined with eForth. |
- | + | You may order the **full | |
- | Chen-Hanson Ting, \\ | + | \\ |
+ | \\ | ||
+ | You can read quite a bit of description | ||
+ | [[https:// | ||
+ | \\ | ||
+ | {{: | ||
+ | \\ | ||
+ | Chen-Hanson Ting,\\ | ||
San Mateo, California\\ | San Mateo, California\\ | ||
February, 2017\\ | February, 2017\\ | ||
- | {{: | + | ===== ASIC Implementation ===== |
- | ===== Target Boards ===== | + | An [[http:// |
+ | – we are waiting for an official confirmation statement | ||
- | Our VHDL can be easily adapted to run on other FPGAs. As well a good project to compare different FPGA families and suppliers for performance and power consumption. | + | And google might reveal some more activities about Chen-Hanson Ting’s |
- | Its first Implementation was on Lattice Brevia Board. One of our additional targets is the Trenz Computer Xilinx 40 Pin Zynq Board as it is the size of a 40 Pin DIP and low cost. | + | ===== Code Image Example ===== |
- | {{: | + | The Code Image Example ready to Program the Brevia Board |
+ | will be added as soon as available. This will set up the FPGA and as well program in the eForth software. | ||
+ | After Flashing it in, just open your favourite Terminal Program and you can start programming in eForth via the same USB cable – no extra hardware. | ||
+ | |||
+ | ===== A short PowerPoint Presentation of the EP32 Target Boards ===== | ||
+ | |||
+ | Ting’s VHDL can be easily adapted to run on many FPGAs. As well it is a good project to compare different FPGA families and suppliers for performance and power consumption. Here is his {{: | ||
+ | At the time tested on:\\ | ||
+ | **Xilinx Virtex II - Actel ProASIC - Altera Stratix II** | ||
+ | |||
+ | |||
+ | ===== The first Code will be for the low-cost Lattice Brevia Board ===== | ||
+ | |||
+ | Its first Implementation is on the | ||
+ | [[http:// | ||
+ | {{: | ||
+ | \\ | ||
+ | |||
+ | ==== Xilinx 40 Pin Zynq Board ==== | ||
+ | |||
+ | One of our additional targets is the Trenz Computer Xilinx 40 Pin Zynq Board as it is the size of a 40 Pin DIP and low cost.\\ | ||
{{: | {{: | ||
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===== Regarding Forth ===== | ===== Regarding Forth ===== | ||
- | [[https:// | + | [[https:// |
- | [[https:// | + | [[https:// |
projects/ep32/start.1492332553.txt.gz · Zuletzt geändert: 2017-04-16 10:49 von mka