pfw:clavis
Unterschiede
Hier werden die Unterschiede zwischen zwei Versionen angezeigt.
Beide Seiten der vorigen RevisionVorhergehende ÜberarbeitungNächste Überarbeitung | Vorhergehende Überarbeitung | ||
pfw:clavis [2025-06-14 23:12] – [Background information] mka | pfw:clavis [2025-06-15 08:43] (aktuell) – [Background information] topic of bouncing added mka | ||
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Zeile 5: | Zeile 5: | ||
Forth has '' | Forth has '' | ||
- | {{: | + | {{: |
Zeile 22: | Zeile 22: | ||
| | ||
configure pin as input | configure pin as input | ||
- | | + | |
check for falling edge at pin | check for falling edge at pin | ||
Zeile 28: | Zeile 28: | ||
==== Forth implementation (noForth) ==== | ==== Forth implementation (noForth) ==== | ||
- | The port pins are configured using registers. | + | The port pins are configured using registers. |
The configuration register table is specified in the code. | The configuration register table is specified in the code. | ||
The interrupt register indicates whether a falling edge was present. | The interrupt register indicates whether a falling edge was present. | ||
Zeile 34: | Zeile 34: | ||
In the direction register, P1.7 is set to digital IN. | In the direction register, P1.7 is set to digital IN. | ||
The integrated pull-up resistor is activated to support the high level. | The integrated pull-up resistor is activated to support the high level. | ||
- | The integrated | + | The integrated |
However, no interrupt should occur, so it is disabled. | However, no interrupt should occur, so it is disabled. | ||
The pin is used in the I/O function. | The pin is used in the I/O function. | ||
Zeile 118: | Zeile 118: | ||
=== What is a Port? === | === What is a Port? === | ||
+ | |||
+ | In short: The " | ||
See: Texas Instruments MSP430F2xx, MSP430G2xx Family User’s Guide - 8 Digital I/O, p.339ff | See: Texas Instruments MSP430F2xx, MSP430G2xx Family User’s Guide - 8 Digital I/O, p.339ff | ||
- | In short: | + | === How long is a key press? === |
+ | |||
+ | A manual | ||
+ | |||
+ | {{:pfw: | ||
+ | |||
+ | As you can see in the image, the key //bounces// briefly at the beginning until a stable LOW state is reached. | ||
+ | |||
+ | {{: | ||
+ | |||
+ | In the second image, the bounce phase has been enlarged. After about 1ms, the bouncing was over. | ||
+ | |||
+ | The port pin reacts to the first falling | ||
+ | |||
+ | More on the [[pfw: | ||
pfw/clavis.1749935560.txt.gz · Zuletzt geändert: 2025-06-14 23:12 von mka