Direct Threaded Code

Gegeben sei eine Forth Wort Definition:

: name	  word1 word2 word3 ;

Bei Direct Threaded Code ergibt sich daraus der folgende Aufbau der Liste:

header with nameJMP NESTZeiger auf word1Zeiger auf word2Zeiger auf word3Zeiger auf EXIT

Der Inner Interpreter für Direct Threaded Code sieht dann so aus (pseudo-code):

Next  W <- (IP)
      JMP (W)

oder kürzer:

Next  JMP (IP)++

Dazu gab es einen englischen Komentar:

On Intel x86 or 6502/65816, the JMP NEST instruction *may* be substituted with a CALL NEST instead. This places the address of „ptr to word1“ on the CPU's hardware stack, where it is easily processed by NEST.

The body of the definition consists of pointers to the parameter fields of each word, where CPU-executable code is always found in some capacity or another.

The inner interpreter for DirectThreadedCode looks like this (pseudo-code):

NEST:	 ; For JMP-based systems
	 -(RSP) <- IP
	 IP <- W + sizeof(JMP)
	 JMP Next

NEST:	 ; For CALL-based systems
	 -(RSP) <- IP
	 JMP Next

EXIT:	 ; For both types
	 IP <- (RSP)+
	 JMP Next

	 W <- (IP)
	 JMP (W)

For architectures that support automatic post-increment on a memory access, it can be significantly simplified at the expense of maintaining the W pseudo-register:

	JMP (IP)++
words/axiome/threaded-code/directthreadedcode.txt · Zuletzt geändert: 2010-12-29 18:12 (Externe Bearbeitung)