\ ADC input Versuche
  
  hex
  01B0 CONSTANT ADC10CTL0
  01B2 CONSTANT ADC10CTL1
  01B4 CONSTANT ADC10MEM
  004A CONSTANT ADC10AE0
  
  bin
  \ FEDCBA9876543210
  \   1               SREF_1      1*0x2000 VREF+ and VR- 
  \    1              ADC10SHT_2  2*0x800  16 x ADC10CLKs
  \          1        REF2_5V     0x040    ADC10 Ref 0:1.5V / 1:2.5V 
  \           1       REFON       0x020    Reference on
  \            1      ADC10ON     0x010    ADC10 On/Enable 
    0011000001110000  CONSTANT ADCSETUP
  
    0000000000000010  CONSTANT ENC      \ Enable Conversion.
    0000000000000001  CONSTANT ADC10SC  \ sample-and-conversion start.
    0000000000000100  CONSTANT ADC10IFG
    0100000000000000  CONSTANT INCH4    \ input chanel 4
  
    00000001 CONSTANT BIT0
    00000010 CONSTANT BIT1
    00000100 CONSTANT BIT2
    00001000 CONSTANT BIT3
    00010000 CONSTANT BIT4
    00100000 CONSTANT BIT5
    01000000 CONSTANT BIT6
    10000000 CONSTANT BIT7
    
  : ADC-INIT
    adcsetup ADC10CTL0 !
    inch4 ADC10CTL1 !        \ input channel 4
    bit4  ADC10AE0  c! ;     \ Analog Input Enable P1.4 = CA4
  : ADC+   1 ADC10CTL0 cset ;  \ Start ADC10  
  : ADC-   1 ADC10CTL0 cclr ;  \ STOP ADC10 
  : ADC \  -- adcmem       sample & convert once
    ENC ADC10SC +  ADC10CTL0 cset  
    BEGIN ADC10IFG ADC10CTL0 cget UNTIL adc10mem ;
  
  hex  variable MINIMUM   variable MAXIMUM 
  
  : INIT     
    bit1 bit2 + p2 1+ cset  \ P2.1 und P2.2 sind output
    bit4        p1 1+ cclr  \ P1.4 is input
    adc- adc-init adc+ 
    FFFF minimum !   0 maximum !  ;
  
  decimal  
  : range   ( n -- )
    dup minimum @ umin minimum !
        maximum @ umax maximum ! ;
  : .adc      
    00 00 at-xy ."                                    "  \ <-- löscht Zeile 
    00 00 at-xy ." min " minimum @ u. 
    10 00 at-xy ." adc " adc @ dup u. range 
    20 00 at-xy ." max " maximum @ u. 
    30 00 at-xy ." dif " maximum @ minimum @ - u. ;
  
  : TEST      init page BEGIN  1000 ms .adc  key? UNTIL ;
  
  : .DATA   init 50 0  DO cr adc @ u. LOOP ;
  : .DATA2  init 50 0  DO cr 100 ms adc @ u. LOOP ;
    
  ( finis )